1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit (IC) chip and packaging assemblies thereof and, more particularly, to IC chips or dies having stepped, modified or otherwise non-rectangular peripheries and related single-chip or multi-chip packages incorporating one or more such IC chips in combination with other such IC chips and/or conventional IC chips.
2. Description of the Related Art
In general, semiconductor products are manufactured through three main process groupings or categories; i.e., wafer fabrication, package assembly, and test. Wafer fabrication typically includes all processing steps, e.g., thermal processing, ion implantation, deposition, planarizing, photolithography and etching, necessary to take a bare semiconductor wafer or other suitable substrate and create a number of integrated circuit (IC) devices in and on a primary surface.
After wafer fabrication has been completed and, in some instances, some preliminary parametric and/or functional testing has been performed, the semiconductor wafer will undergo a wafer dicing process. During this process, the thickness of the semiconductor wafer will typically be reduced by removing a backside portion and portions of the wafer below the scribe lines or kerf regions provided between adjacent IC chips is removed or split to separate the individual IC chips from each other. The wafer dicing process is also sometimes referred to as a wafer sawing or wafer scribing process.
Once the individual IC chips have been separated from the semiconductor wafer, they may assembled to form a final device package by, for example, attaching an IC chip to a substrate, such as a lead frame, that will provide for external connection to IC chip to a circuit board or socket. The IC chip and at least a portion of the substrate and the electrical connections formed between the chip and the substrate will typically be encapsulated for improving the resistance of the device package to mechanical damage and contamination from the external environment. The final device package may include one or more IC chips and, in the case of a multi-chip package, may include chips that are substantially identical or may include chips having a variety of functions and/or sizing. For example, a multi-chip package may be configured to include both a microprocessor IC chip coupled with a memory chip in a single package.
Most conventional IC chips have a generally square or rectangular shape when observed in a plan view. This configuration is due, at least in part, to the conventional wafer dicing technique which is shown in FIG. 1. As illustrated in FIG. 1, the dicing machine moves a rotating dicing blade 14 along the scribe lines S provided between adjacent rectangular IC chips 12 formed on semiconductor wafer 10. Because the cut length of the dicing blade 14 is typically at least a significant fraction of the lengths of the sides of the IC chips 12, the dicing machine is typically limited to making long, straight cuts and cannot effectively or efficiently cut more complex IC chip profiles. Accordingly, conventional IC chip profiles are almost exclusively rectangular, although triangular or non-rectangular parallelogram profiles are also possible.
An alternative dicing technique has been developed that utilizes a laser scriber rather than the conventional dicing blade to address some of the problems associated with dicing blades, such as chipping, that can reduce device yield and/or reliability. A laser dicing or scribing technique is, for example, taught in Applicants previous U.S. patent application Ser. No. 10/805,212, for forming non-rectangular IC chip profiles. For example, a Mahoh Dicing Machine, available from Tokyo Seimitsu Co., Ltd., may be utilized for cutting semiconductor wafers using a non-contact method that tends to reduce or eliminate the damage to the wafer surface associated with conventional sawing. Specifically, the laser dicer focuses a laser beam on a subsurface region of the semiconductor wafer to form a modified region that tends to grow or propagate vertically along a narrow width for separating IC chips while reducing damage, such as chipping, associated with removing a portion of the wafer with abrasives as in conventional sawing techniques.
The generally square or rectangular shape of the conventional IC chip tends to be reflected in the shape of the packages incorporating such IC chips, whether the package is a single-chip package or a multi-chip package. Because the shape of the conventional packages, like the conventional IC chips, is generally square or rectangular, the sizing of the various packages mounted on a single substrate, such as a circuit board, may reduce the packing density that may be obtained and/or increase the size of the substrate required to mount all of the intended IC chips.
Moreover, the conventional square or rectangular shape of the IC chips may complicate efforts to reduce the overall height or thickness of multi-chip packages. For example, when two IC chips are stacked, if the upper chip is of a size that will obstruct one or more bond pads on the lower chip, a suitable spacer must be inserted between the chips to ensure that the bond pads of the lower chip remain accessible. As illustrated in FIG. 3A, however, incorporating a spacer will tend to increase the overall thickness of the resulting chip stack by a dimension S2.
One approach for addressing this interference between the upper and lower IC chips has been to remove a lower peripheral portion of the upper chip to form a recessed opening of sufficient size to permit wire bonding to the bond pads of the lower chip as illustrated in FIG. 3B. However, because portions of the upper chip are thinned, this technique may introduce additional problems by increasing the likelihood that the weaker cantilevered portion of the upper chip may be cracked or broken during wire bonding when compared with the performance of a corresponding full thickness chip.
Another approach for addressing the obstruction of the bond pads on the lower chip is rotating the upper chip with respect to the lower chip to provide for a “diagonal” mounting orientation and thereby expose additional wire-bonding areas on the lower chip. This technique is, however, somewhat limited in the range of relative chip sizes and orientations for which improved access to the lower chip bond pads is achieved without also creating significant cantilevered portions that would be more susceptible to mechanical damage, increasing the overall package size, and/or increasing the complexity of the apparatus and/or control device used to achieve the offset alignment.